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    A Light Reading Webinar:

    Future Coherent Interconnect Technology for Networking Applications


    Duration: 60 minutes

    Coherent interconnects will be at the core of next-generation network systems and system-on-chip (SoC) devices. To meet the rapidly growing processing requirements of wireless infrastructure systems and servers, network equipment manufacturers need highly integrated SoCs with a heterogeneous mix of CPU cores. These cores need to handle a mix of general-purpose processing, packet processing, and digital signal processing (DSP) functions. The interconnect at the center of these solutions must maintain cache coherency between cores and provide a low-latency path between the cores, caches, external memory, and networking I/O.

    This webinar will explore the market demands and benefits of using a low-latency, coherent interconnect at the core of a next-generation networking SoC with multiple CPU cores and hardware accelerators. It details the technical challenges and looks at a solution for a coherent interconnect with integrated cache and support for DDR3 and DDR4 memories. This webinar also describes a next-generation networking SoC architecture built around a coherent interconnect and available to OEMs as a standard product or custom solution.


     
     

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